Hardware Engineer
Sebastian Sholl
Hardware engineer with expertise in high-end ASIC methodology and design. Experienced in delivering tools, flows, and design automation to enable reliable, tapeout-ready designs.
About
Hi! I’m Sebastian, a Top Level Physical Design Engineer at Apple, and formerly Intel and Cray. I value team collaboration, clear communication, and constant feedback to further my own growth and the growth of those around me.
I’m currently based in the Austin area, but have previously lived in Minneapolis, Boston, Nagasaki, and many parts of Wisconsin. I enjoy spending time with my lovely wife and two awesome dogs. When I’m not working I have fun gaming, maintaining the home lab, cooking, and trying to travel as often as possible.
Professional Experience
Download Resume (PDF)- Interfaced with central design automation and cross-organizational teams to integrate converged tools and flows into the Omni-Path second-generation environment. Deployed two physical design environments used by cross-site teams across three Omni-Path ASICs.
- Developed a verification environment for centralized signoff of blocks and full-chip designs, providing a “known good” configuration that decreased time needed for chip convergence.
- Execution owner for the chassis block on the second-generation Omni-Path ASIC, integrating multiple SIPs and HIPs delivered from across the organization; an extremely challenging design for constraint, clocking, and physical layout.
- Member of the tapeout team for first-generation Omni-Path ASICs. Drove block and full-chip LVS, DRC, ERC, and antenna closure, developing methods for correct-by-construction, quick RTL-to-GDS and ECO turns.
- Promoted best-known practices by championing project and flow documentation; provided frequent training and mentored junior engineers.
- Execution owner for two large hierarchical blocks in the first-generation Omni-Path Switch ASIC. Led back-end tools, flows, and methodologies; directed meetings, tracked progress, and drove methodology across the physical design team.
- Designed and deployed a methodology to generate physical design kits for multiple ASICs; integrated IP deliveries for logic, verification, and physical design teams.
- Managed design databases and collateral for multiple ASICs with a custom design repository tool supporting top-down and bottom-up hierarchical methodologies; introduced contouring to handle interface changes and cut full-chip model build time.
- Worked closely with IT to maintain and deploy wiki, SharePoint, bug tracking, compute, and disk resources for the Omni-Path organization.
- Pushed physical design quality checks earlier into logic design development to enable a constant-integration handoff model between front and back end.
- Back-end flow developer for the Pisces 28 nm NIC ASIC; deployed multi-corner multi-mode synthesis and automatic place-and-route flows.
- Responsible for integration of internal and external HIPs within the back-end design environment; drove resolution of library issues with HIP providers and automated tool view generation and quality validation.
- Devised a configuration-management and revision-control environment for release of tools and libraries across the back-end design environment.
- Developed a front-end synthesis and basic floorplanning flow for the Pisces logic design team.
- Worked on multiple generations of ASIC routers: Gemini (90 nm, 48-port, 44M-gate) and Aries (40 nm, 217M-gate, 48-port).
- Execution owner for Aries DFT and TAP blocks; developed and debugged scan and MBIST insertion scripting for Aries.
- Owner for DFT linting across Aries and Gemini; worked with logic designers to resolve DFT issues impacting testability and scan coverage.
- Assisted the STA team in resolving block and full-chip DFT timing issues.
- Developed a simulation environment for creation and debug of wafer and package tests, including HT3, MBIST, PLL, JTAG, and PCIe Gen3.
- Collaborated with the external test team to bring manufacturing tests to production; resolved DFT power-consumption issues for MBIST through targeted testing of individual cores.
Tools & Programming
- Software
- Synopsys tools: Design Compiler, IC Compiler, PrimeTime, Spyglass, Formality, TetraMAX, VCS, IC Validator
- Revision control
- Git, Perforce
- Programming
- Perl, Tcl/Tk, SQL, Unix, XML, XHTML
- HDL
- SystemVerilog, Verilog
Education
University of Wisconsin–Platteville
B.S., Electrical Engineering, December 2006
Emphasis: Computer Engineering, Power & Energy Distribution
- Eta Kappa Nu, Electrical Engineering Honor Society (Spring 2003)
- Tau Beta Pi, National Engineering Honor Society (Spring 2003)
Contact
Feel free to reach out with any questions or comments. I’m available by phone or email.
- Email sholls@gmail.com
- Phone 608.772.2287
- LinkedIn /in/sebastian-sholl
- Location Austin area, Buda, TX